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| author | Craig Topper <craig.topper@intel.com> | 2019-08-26 18:23:26 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-08-26 18:23:26 +0000 |
| commit | 36d1588f017bb6e971cb14cc6e7094c3db9c0436 (patch) | |
| tree | 1a3fa37ca359557e1cf523e99ac2e47d51ddfd25 /lldb/packages/Python/lldbsuite/test/python_api/value/main.c | |
| parent | ac1d5986c836924896aeb934ff71432f80c70063 (diff) | |
| download | bcm5719-llvm-36d1588f017bb6e971cb14cc6e7094c3db9c0436.tar.gz bcm5719-llvm-36d1588f017bb6e971cb14cc6e7094c3db9c0436.zip | |
[X86] Add a hack to combinePMULDQ to manually turn SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG inputs into an ANY_EXTEND_VECTOR_INREG style shuffle
ANY_EXTEND_VECTOR_INREG isn't currently marked Legal which prevents SimplifyDemandedBits from turning SIGN/ZERO_EXTEND_VECTOR_INREG into it after op legalization. And even if we did make it Legal, combineExtInVec doesn't do shuffle combining on the VECTOR_INREG nodes until AVX1.
This patch adds a quick hack to combinePMULDQ to directly emit a vector shuffle corresponding to an ANY_EXTEND_VECTOR_INREG operation. This avoids both of those issues without creating any other regressions on our tests. The xop-ifma.ll change here also showed up when I tried to resurrect D56306 and seemed to be the only improvement that patch creates now. This is a more direct way to get the benefit.
Differential Revision: https://reviews.llvm.org/D66436
llvm-svn: 369942
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/value/main.c')
0 files changed, 0 insertions, 0 deletions
