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| author | Craig Topper <craig.topper@intel.com> | 2018-11-27 02:57:23 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-27 02:57:23 +0000 |
| commit | fe3bbb251b52b79243c69365127fa919f1ec1584 (patch) | |
| tree | ca306ceecf0b2837cc6c07821faa293d8ee8b5d5 /lldb/packages/Python/lldbsuite/test/python_api/value/TestValueAPI.py | |
| parent | 0ef5843dcc1450c3a422aea4567e71fc7a325950 (diff) | |
| download | bcm5719-llvm-fe3bbb251b52b79243c69365127fa919f1ec1584.tar.gz bcm5719-llvm-fe3bbb251b52b79243c69365127fa919f1ec1584.zip | |
[X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type.
Currently a store combine will absorb the bitcast before our combine that turns bitcasts into movmsk gets a chance to run. This results in a store being created with a vXi1 type. Type legalization then promotes the input type and makes this a truncating store. Then we badly scalarize this store.
Currently we avoid this on v8i1->i8 bitcasts due to an incompletely qualified(per the original intention) check in isLoadBitCastBeneficial. An easy fix is to disable this for all vXi1->iX bitcasts on pre-avx512 targets. We'll still generate terrible code if the IR explicitly contains a store of vXi1 without a bitcast. We could probably solve that by just turning all stores of vXi1 into (store (iX (bitcast))) as an early DAG combine.
llvm-svn: 347631
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/value/TestValueAPI.py')
0 files changed, 0 insertions, 0 deletions
