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authorSimon Tatham <simon.tatham@arm.com>2019-11-15 09:53:15 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-11-15 09:53:58 +0000
commit9e37892773c0954a15f84b011223da1e707ab3bf (patch)
treed3aec012c1d6f5633cf81c408a5146b87903e59c /lldb/packages/Python/lldbsuite/test/python_api/value/TestValueAPI.py
parent902e84556a51c70d95088aaa059ab9c494ab3516 (diff)
downloadbcm5719-llvm-9e37892773c0954a15f84b011223da1e707ab3bf.tar.gz
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[ARM,MVE] Add intrinsics for vector get/set lane.
This adds the `vgetq_lane` and `vsetq_lane` families, to copy between a scalar and a specified lane of a vector. One of the new `vgetq_lane` intrinsics returns a `float16_t`, which causes a compile error if `%clang_cc1` doesn't get the option `-fallow-half-arguments-and-returns`. The driver passes that option to cc1 already, but I've had to edit all the explicit cc1 command lines in the existing MVE intrinsics tests. A couple of fixes are included for the code I wrote up front in MveEmitter to support lane-index immediates (and which nothing has tested until now): the type was wrong (`uint32_t` instead of `int`) and the range was off by one. I've also added a method of bypassing the default promotion to `i32` that is done by the MveEmitter code generation: it's sensible to promote short scalars like `i16` to `i32` if they're going to be passed to custom IR intrinsics representing a machine instruction operating on GPRs, but not if they're going to be passed to standard IR operations like `insertelement` which expect the exact type. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70188
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