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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-03 06:57:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-03 06:57:55 +0000 |
| commit | 2510a316773cb7128554bcecc8d209abef326c78 (patch) | |
| tree | acad5a8f18ca6ff6e267440e7a0a9bfac3af86b6 /lldb/packages/Python/lldbsuite/test/python_api/value/TestValueAPI.py | |
| parent | f3d1a1a1b6b57e6030f0719c358fa08f25558013 (diff) | |
| download | bcm5719-llvm-2510a316773cb7128554bcecc8d209abef326c78.tar.gz bcm5719-llvm-2510a316773cb7128554bcecc8d209abef326c78.zip | |
AMDGPU: Fix spilling of m0
readlane/writelane do not support using m0 as the output/input.
Constrain the register class of spill vregs to try to avoid this,
but also handle spilling of the physreg when necessary by inserting
an additional copy to a normal SGPR.
llvm-svn: 280584
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/value/TestValueAPI.py')
0 files changed, 0 insertions, 0 deletions
