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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2019-05-13 09:47:26 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2019-05-13 09:47:26 +0000
commit8e42f6ddc80f56e36264b1ec0f2d88df8486331e (patch)
tree0bc749f67964850d0b7a69a9238b01c88a1da654 /lldb/packages/Python/lldbsuite/test/python_api/thread
parent869f934d19f76189821caccfc0d93a3bcdf4f182 (diff)
downloadbcm5719-llvm-8e42f6ddc80f56e36264b1ec0f2d88df8486331e.tar.gz
bcm5719-llvm-8e42f6ddc80f56e36264b1ec0f2d88df8486331e.zip
[SystemZ] Model floating-point control register
This adds the FPC (floating-point control register) as a reserved physical register and models its use by SystemZ instructions. Note that only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the FPC due to exceptions (in particular the IEEE exception flags and the DXC) are not modeled. At this point, this patch is mostly NFC, but it will prevent scheduling of floating-point instructions across SPFC/LFPC etc. llvm-svn: 360570
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