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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-10 17:19:46 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-10 17:19:46 +0000 |
| commit | e1895aba3da01df442253bf048e38371377db15e (patch) | |
| tree | a961bae49e9391414f9c3596d13e1dbb8d93d65b /lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp | |
| parent | 7df5b3fd26243a80d97382fdc09ce0374ab98d87 (diff) | |
| download | bcm5719-llvm-e1895aba3da01df442253bf048e38371377db15e.tar.gz bcm5719-llvm-e1895aba3da01df442253bf048e38371377db15e.zip | |
AMDGPU/GlobalISel: Select G_FABS/G_FNEG
f64 doesn't work yet because tablegen currently doesn't handlde
REG_SEQUENCE.
This does regress some multi use VALU fneg cases since now the
immediate remains in an SGPR, and more moves are used for legalizing
the xor. This is a SIFixSGPRCopies deficiency.
llvm-svn: 371540
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp')
0 files changed, 0 insertions, 0 deletions
