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| author | Simon Dardis <simon.dardis@mips.com> | 2018-02-20 23:49:17 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-02-20 23:49:17 +0000 |
| commit | cd8758233ebacf36b373481a1dc1e025ee487a39 (patch) | |
| tree | e4db450c893e214e3517eb353365a852fe27b5df /lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp | |
| parent | 148bc6a1f79b0d9a7e6651ce1b2252d0b540db6c (diff) | |
| download | bcm5719-llvm-cd8758233ebacf36b373481a1dc1e025ee487a39.tar.gz bcm5719-llvm-cd8758233ebacf36b373481a1dc1e025ee487a39.zip | |
[mips][lld] Spectre variant two mitigation for MIPSR2
This patch provides migitation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLD part of
-z hazardplt. Like the Clang part of this patch, I have opted for that
specific option name in case alternative migitation methods are required
in the future.
The mitigation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
For LLD, this changes PLT stubs to use 'jalr.hb' and 'jr.hb'.
Reviewers: atanasyan, ruiu
Differential Revision: https://reviews.llvm.org/D43488
llvm-svn: 325647
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp')
0 files changed, 0 insertions, 0 deletions
