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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-10-14 11:12:18 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-10-14 11:12:18 +0000 |
| commit | b744abb4f6a94926b1ed15b9c3bf56bce9aae28d (patch) | |
| tree | fcde1c0d051986afd527653708b3ddb7bdd35d71 /lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp | |
| parent | 527a35e1555834c9890eefde8d9edd885f9ae57f (diff) | |
| download | bcm5719-llvm-b744abb4f6a94926b1ed15b9c3bf56bce9aae28d.tar.gz bcm5719-llvm-b744abb4f6a94926b1ed15b9c3bf56bce9aae28d.zip | |
[X86][BtVer2] Improved latency and throughput of float/vector loads and stores.
This patch introduces the following changes to the btver2 scheduling model:
- The number of micro opcodes for YMM loads and stores is now 2 (it was
incorrectly set to 1 for both aligned and misaligned loads/stores).
- Increased the number of AGU resource cycles for YMM loads and stores
to 2cy (instead of 1cy).
- Removed JFPU01 and JFPX from the list of resources consumed by pure
float/vector loads (no MMX).
I verified with llvm-exegesis that pure XMM/YMM loads are no-pipe. Those
are dispatched to the FPU but not really issues on JFPU01.
Differential Revision: https://reviews.llvm.org/D68871
llvm-svn: 374765
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/thread/main.cpp')
0 files changed, 0 insertions, 0 deletions
