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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-11-05 01:12:10 +0300 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-11-07 13:58:50 +0300 |
| commit | 7bed381eae12277d6e0ef7e8a56491d11589ee7f (patch) | |
| tree | 25d051534dfdf1218c41f673bef6590ff0121824 /lldb/packages/Python/lldbsuite/test/python_api/target/TestTargetAPI.py | |
| parent | eaff3004019f97c64c88ab76da6b25106b659b30 (diff) | |
| download | bcm5719-llvm-7bed381eae12277d6e0ef7e8a56491d11589ee7f.tar.gz bcm5719-llvm-7bed381eae12277d6e0ef7e8a56491d11589ee7f.zip | |
[mips] Implement Octeon+ `saa` and `saad` instructions
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.
memory[base] = memory[base] + rt
These instructions are available for "Octeon+" CPU. The patch adds support
for both instructions to MIPS assembler and diassembler and introduces new
CPU type - "octeon+".
Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP`
ISA extension flag support.
Differential Revision: https://reviews.llvm.org/D69849
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/target/TestTargetAPI.py')
0 files changed, 0 insertions, 0 deletions
