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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-21 15:48:13 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-21 15:48:13 +0000 |
| commit | 8df2f3dab203acbb84e6a9c88433f13fc62d573d (patch) | |
| tree | c8a5be1a7d3658cf188b4cabaa1cec969422656d /lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp | |
| parent | e1cbabaff0498efb40ff1f96c32fe95adbc8a49e (diff) | |
| download | bcm5719-llvm-8df2f3dab203acbb84e6a9c88433f13fc62d573d.tar.gz bcm5719-llvm-8df2f3dab203acbb84e6a9c88433f13fc62d573d.zip | |
RegBankSelect: Allow targets to introduce control flow for mapping
For AMDGPU, if an operand requires an SGPR but is only available as a
VGPR, a loop needs to be introduced to execute the instruction with
each unique combination of values across all lanes. The rest of the
instructions in the block will be moved to a new block following the
loop. Check if the next instruction's parent changed, and update the
iterators and insertion block if this happened.
Tests will be included in a future patch.
llvm-svn: 354591
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp')
0 files changed, 0 insertions, 0 deletions
