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author | Hal Finkel <hfinkel@anl.gov> | 2016-09-03 02:31:44 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2016-09-03 02:31:44 +0000 |
commit | 522e4d9d66c08b7f7471e7093622f3be0ef1c9a3 (patch) | |
tree | 7beae965695ef537028332bfb901cf12a5e83e0e /lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp | |
parent | 4e229a7c0a261614dd9ed2a473dde32e8ff69925 (diff) | |
download | bcm5719-llvm-522e4d9d66c08b7f7471e7093622f3be0ef1c9a3.tar.gz bcm5719-llvm-522e4d9d66c08b7f7471e7093622f3be0ef1c9a3.zip |
[PowerPC] Support asm parsing for bc[l][a][+-] mnemonics
PowerPC assembly code in the wild, so it seems, has things like this:
bc+ 12, 28, .L9
This is a bit odd because the '+' here becomes part of the BO field, and the BO
field is otherwise the first operand. Nevertheless, the ISA specification does
clearly say that the +- hint syntax applies to all conditional-branch mnemonics
(that test either CTR or a condition register, although not the forms which
check both), both basic and extended, so this is supposed to be valid.
This introduces some asm-parser-only definitions which take only the upper
three bits from the specified BO value, and the lower two bits are implied by
the +- suffix (via some associated aliases).
Fixes PR23646.
llvm-svn: 280571
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp')
0 files changed, 0 insertions, 0 deletions