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| author | James Clarke <jrtc27@jrtc27.com> | 2020-01-13 00:50:37 +0000 |
|---|---|---|
| committer | James Clarke <jrtc27@jrtc27.com> | 2020-01-13 00:50:37 +0000 |
| commit | 0113cf193f0610bb1a5dfa0bcd29c41a8965938a (patch) | |
| tree | 0495e335b6a396cbe256dbfa7c46fc161fd77200 /lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp | |
| parent | 54b2914accb4f5c9b58305fd6da405d20a47c452 (diff) | |
| download | bcm5719-llvm-0113cf193f0610bb1a5dfa0bcd29c41a8965938a.tar.gz bcm5719-llvm-0113cf193f0610bb1a5dfa0bcd29c41a8965938a.zip | |
[RISCV] Check register class for AMO memory operands
Summary:
AMO memory operands use a custom parser in order to accept both (reg)
and 0(reg). However, the validation predicate used for these operands
was only checking that they were registers, and not the register class,
so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making
the predicate check that they are GPRs.
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72471
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/main.cpp')
0 files changed, 0 insertions, 0 deletions
