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authorCraig Topper <craig.topper@intel.com>2019-12-24 11:08:06 -0800
committerCraig Topper <craig.topper@intel.com>2019-12-24 11:20:10 -0800
commitc06e53119b1f04696fbcf710aaa0818cbfc99600 (patch)
tree100ada107505940ab28967dbe3ff70a1987768e5 /lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py
parent020ca0cf2f1470db24fe0e194467a66fdea73795 (diff)
downloadbcm5719-llvm-c06e53119b1f04696fbcf710aaa0818cbfc99600.tar.gz
bcm5719-llvm-c06e53119b1f04696fbcf710aaa0818cbfc99600.zip
[X86] Use 128-bit vector instructions for f32/f64->i64 conversions on 32-bit targets with avx512dq and avx512vl instructions.
On 32-bit targets we can't use the scalar instruction so we insert the scalar into a vector and use packed conversions. Previously we used either v4f32->v4i64 or v4f64->v4i64 to avoid some complexity creating target specific ISD opcodes for v4f32->v2i64. But this causes extra vzeroupper instructions and possibly frequency throttling on Intel CPUs. This patch changes this to create a 128-bit vector and uses a target specific ISD opcode if needed.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py')
0 files changed, 0 insertions, 0 deletions
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