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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-14 11:51:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-14 11:51:41 +0000 |
| commit | c05a11108b9a9deb266c3c1758677462df61e05e (patch) | |
| tree | a8e63f33c3d318e1758864d8a027180340fd4201 /lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py | |
| parent | bad6032bc15fa8d16b67b86ef2b2fe48724e756e (diff) | |
| download | bcm5719-llvm-c05a11108b9a9deb266c3c1758677462df61e05e.tar.gz bcm5719-llvm-c05a11108b9a9deb266c3c1758677462df61e05e.zip | |
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.
As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed bottom zero bits from the shifted value, and then, if a min shift amount is known, zero out the bottom bits as well.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py')
0 files changed, 0 insertions, 0 deletions
