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| author | Sanjay Patel <spatel@rotateright.com> | 2019-09-11 12:04:26 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-09-11 12:04:26 +0000 |
| commit | 80bea345d11912c6473797fcea0866a7f0ca9cca (patch) | |
| tree | f9b89f38c2eab5ac277b9a1b4a6fc1e8c47825e9 /lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py | |
| parent | 48904e9452de81375bd55d830d08e51cc8f2ec7e (diff) | |
| download | bcm5719-llvm-80bea345d11912c6473797fcea0866a7f0ca9cca.tar.gz bcm5719-llvm-80bea345d11912c6473797fcea0866a7f0ca9cca.zip | |
[InstCombine] fold sign-bit compares of srem
(srem X, pow2C) sgt/slt 0 can be reduced using bit hacks by masking
off the sign bit and the module (low) bits:
https://rise4fun.com/Alive/jSO
A '2' divisor allows slightly more folding:
https://rise4fun.com/Alive/tDBM
Any chance to remove an 'srem' use is probably worthwhile, but this is limited
to the one-use improvement case because doing more may expose other missing
folds. That means it does nothing for PR21929 yet:
https://bugs.llvm.org/show_bug.cgi?id=21929
Differential Revision: https://reviews.llvm.org/D67334
llvm-svn: 371610
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py')
0 files changed, 0 insertions, 0 deletions
