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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-02-03 09:41:59 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-02-03 09:41:59 +0000 |
| commit | 18bcf93efb3b5c99fba6d95e197b8f26538e5a48 (patch) | |
| tree | eaf08f12851f90554f1147b4b0675912593b7ca8 /lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py | |
| parent | 75f0ff5ba1826e157f8da6756f644560586e5637 (diff) | |
| download | bcm5719-llvm-18bcf93efb3b5c99fba6d95e197b8f26538e5a48.tar.gz bcm5719-llvm-18bcf93efb3b5c99fba6d95e197b8f26538e5a48.zip | |
[X86][AVX] Add support for 64-bit VZEXT_LOAD of 256/512-bit vectors to EltsFromConsecutiveLoads
Follow up to D16217 and D16729
This change uncovered an odd pattern where VZEXT_LOAD v4i64 was being lowered to a load of the lower v2i64 (so the 2nd i64 destination element wasn't being zeroed), I can't find any use/reason for this and have removed the pattern and replaced it so only the 1st i64 element is loaded and the upper bits all zeroed. This matches the description for X86ISD::VZEXT_LOAD
Differential Revision: http://reviews.llvm.org/D16768
llvm-svn: 259635
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py')
0 files changed, 0 insertions, 0 deletions
