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authorSam Parker <sam.parker@arm.com>2019-12-12 14:30:09 +0000
committerSam Parker <sam.parker@arm.com>2019-12-12 14:34:00 +0000
commit1274ac3dc235dd596cc1ace2145c2b1e3c970b29 (patch)
tree027d98937098d8cb9f6c5a83f7d4dda417829484 /lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py
parent6ce1a897b6a82e18059fd3b75b8d52ff12c2a605 (diff)
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[ARM][MVE] Sink vector shift operand
Recommit e0b966643fc2. sub instructions were being generated for the negated value, and for some reason they were the register only ones. I think the problem was because I was grabbing the 'zero' from vmovimm, which is a target constant. Now I'm just generating a new Constant zero and so rsb instructions are now generated. Original commit message: The shift amount operand can be provided in a general purpose register so sink it. Flip the vdup and negate so the existing patterns can be used for matching. Differential Revision: https://reviews.llvm.org/D70841
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