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| author | Sam Parker <sam.parker@arm.com> | 2020-01-14 12:02:32 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2020-01-14 12:03:58 +0000 |
| commit | e27632c3026328e41b0d7dbf25631041e979a2f9 (patch) | |
| tree | 78681cb202d1b05ae6b5b3e7a63cc38a8e03f350 /lldb/packages/Python/lldbsuite/test/python_api/section/TestSectionAPI.py | |
| parent | 31aed2e0dad25d43039a9b933b1b95fbdeb27704 (diff) | |
| download | bcm5719-llvm-e27632c3026328e41b0d7dbf25631041e979a2f9.tar.gz bcm5719-llvm-e27632c3026328e41b0d7dbf25631041e979a2f9.zip | |
[ARM][LowOverheadLoops] Allow all MVE instrs.
We have a whitelist of instructions that we allow when tail
predicating, since these are trivial ones that we've deemed need no
special handling. Now change ARMLowOverheadLoops to allow the
non-trivial instructions if they're contained within a valid VPT
block. Since a valid block is one that is predicated upon the VCTP so
we know that these non-trivial instructions will still behave as
expected once the implicit predication is used instead.
This also fixes a previous test failure.
Differential Revision: https://reviews.llvm.org/D72509
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/section/TestSectionAPI.py')
0 files changed, 0 insertions, 0 deletions
