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authorPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-10-15 09:30:08 +0000
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-10-15 09:30:08 +0000
commit599591f3d47cad6d70f2346c9056f4d4bbddff31 (patch)
tree10aa3455adc7b9c7175b04ea806520e2c8c36787 /lldb/packages/Python/lldbsuite/test/python_api/sbstructureddata/TestStructuredDataAPI.py
parentd46ac44ecdc82ac42510e1ce2b9cd90ee2fa7faa (diff)
downloadbcm5719-llvm-599591f3d47cad6d70f2346c9056f4d4bbddff31.tar.gz
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[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store
Add vector MSA register classes to fprb, they are 128 bit wide. MSA instructions use the same registers for both integer and floating point operations. Therefore we only need to check for vector element size during legalization or instruction selection. Add helper function in MipsLegalizerInfo and switch to legalIf LegalizeRuleSet to keep legalization rules compact since they depend on MipsSubtarget and presence of MSA. fprb is assigned to all vector operands. Move selectLoadStoreOpCode to MipsInstructionSelector in order to reduce number of arguments. Differential Revision: https://reviews.llvm.org/D68867 llvm-svn: 374872
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