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| author | David Green <david.green@arm.com> | 2019-12-02 14:47:22 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-12-02 19:57:12 +0000 |
| commit | 57d96ab593dfff39dc6eb8fa5f25eaf64af26ee1 (patch) | |
| tree | 588a831b17cbc17e468054e0fbcbf785971383dd /lldb/packages/Python/lldbsuite/test/python_api/sbdata/main.cpp | |
| parent | 63aff5cd3c83cc1000cf9c85388e62071086dda2 (diff) | |
| download | bcm5719-llvm-57d96ab593dfff39dc6eb8fa5f25eaf64af26ee1.tar.gz bcm5719-llvm-57d96ab593dfff39dc6eb8fa5f25eaf64af26ee1.zip | |
[ARM] Add some VCMP folding and canonicalisation
The VCMP instructions in MVE can accept a register or ZR, but only as
the right hand operator. Most of the time this will already be correct
because the icmp will have been canonicalised that way already. There
are some cases in the lowering of float conditions that this will not
apply to though. This code should fix up those cases.
Differential Revision: https://reviews.llvm.org/D70822
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/sbdata/main.cpp')
0 files changed, 0 insertions, 0 deletions
