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authorSimon Tatham <simon.tatham@arm.com>2019-11-13 15:23:38 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-11-15 09:53:43 +0000
commit902e84556a51c70d95088aaa059ab9c494ab3516 (patch)
treee0ac82fb4fd42fe5985a47536a7c088d95c63152 /lldb/packages/Python/lldbsuite/test/python_api/process
parent87054ec07bd57719b9f66bf0548d7ac8019799f5 (diff)
downloadbcm5719-llvm-902e84556a51c70d95088aaa059ab9c494ab3516.tar.gz
bcm5719-llvm-902e84556a51c70d95088aaa059ab9c494ab3516.zip
[ARM,MVE] Add intrinsics for 'administrative' vector operations.
This batch of intrinsics includes lots of things that move vector data around or change its type without really affecting its value very much. It includes the `vreinterpretq` family (cast one vector type to another); `vuninitializedq` (create a vector of a given type with don't-care contents); and `vcreateq` (make a 128-bit vector out of two `uint64_t` halves). These are all implemented using completely standard IR that's already tested in existing LLVM unit tests, so I've just written a clang test to check the IR is correct, and left it at that. I've also added some richer infrastructure to the MveEmitter Tablegen backend, to make it specify the exact integer type of integer arguments passed to IR construction functions, and wrap those arguments in a `static_cast` in the autogenerated C++. That was necessary to prevent an overloading ambiguity when passing the integer literal `0` to `IRBuilder::CreateInsertElement`, because otherwise, it could mean either a null pointer `llvm::Value *` or a zero `uint64_t`. Reviewers: ostannard, MarkMurrayARM, dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70133
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