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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-02-28 19:10:32 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-02-28 19:10:32 +0000 |
| commit | 2a99fa2c084b1439c7473032f4af0808d5faabc6 (patch) | |
| tree | 7aba74c5537d3f499d2a2e62e5d30fb0eba8425d /lldb/packages/Python/lldbsuite/test/python_api/process | |
| parent | d319674a81ad579d2067013101e50df8ca1cd7d1 (diff) | |
| download | bcm5719-llvm-2a99fa2c084b1439c7473032f4af0808d5faabc6.tar.gz bcm5719-llvm-2a99fa2c084b1439c7473032f4af0808d5faabc6.zip | |
[AMDGPU] added writelane intrinsic
Summary:
For use by LLPC SPV_AMD_shader_ballot extension.
The v_writelane instruction was already implemented for use by SGPR
spilling, but I had to add an extra dummy operand tied to the
destination, to represent that all lanes except the selected one keep
the old value of the destination register.
.ll test changes were due to schedule changes caused by that new
operand.
Differential Revision: https://reviews.llvm.org/D42838
llvm-svn: 326353
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/process')
0 files changed, 0 insertions, 0 deletions
