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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-01-29 21:09:12 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-01-29 21:09:12 +0000 |
| commit | 08464524c34daa350ba4eaafd6231ddc1c3edee0 (patch) | |
| tree | 12ca7a840e60dc80b7783a097f1866130ef798ba /lldb/packages/Python/lldbsuite/test/python_api/process/main.cpp | |
| parent | bf750c80e9dce1b6e2c270adba64fc85f7fbc861 (diff) | |
| download | bcm5719-llvm-08464524c34daa350ba4eaafd6231ddc1c3edee0.tar.gz bcm5719-llvm-08464524c34daa350ba4eaafd6231ddc1c3edee0.zip | |
[ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern
Summary:
Apparently, we missed on constraining register classes of VReg-operands of all the instructions
built from a destination pattern but the root (top-level) one. The issue exposed itself
while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped
into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained,
while nested VTOSIZS (or rather its destination virtual register to be exact) does not.
Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI.
https://bugs.llvm.org/show_bug.cgi?id=35965
rdar://problem/36886530
Patch by Roman Tereshin
Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan
Reviewed By: dsanders, qcolombet, rovka
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42565
llvm-svn: 323692
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/process/main.cpp')
0 files changed, 0 insertions, 0 deletions
