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| author | Jay Foad <jay.foad@amd.com> | 2019-11-15 11:05:39 +0000 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2019-11-15 11:32:11 +0000 |
| commit | c953e061b410163bc54771f186176a92aac04008 (patch) | |
| tree | 171b3a8a1f19b29df614ea156f085993e427abd6 /lldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py | |
| parent | 41d6ad6efddadbb905bd14c53c2731b75f30cca7 (diff) | |
| download | bcm5719-llvm-c953e061b410163bc54771f186176a92aac04008.tar.gz bcm5719-llvm-c953e061b410163bc54771f186176a92aac04008.zip | |
[CodeGen] Increase the size of a SmallVector
The SmallVector reserve() call in
MachineInstrExpressionTrait::getHashValue accounted for over 3% of all
calls to malloc() when I compiled a bunch of graphics shaders for the
AMDGPU target. Its initial size was only enough for machine instructions
with up to 7 operands, but for AMDGPU 8 and 10 operands are very common.
Here's a histogram of number of operands for each call to getHashValue,
gathered from the same collection of shaders:
1 13503
2 254273
3 135781
4 422508
5 614997
6 194953
7 287248
8 1517255
9 31218
10 1191269
11 70731
12 24
13 77
15 84
17 4692
27 16
33 705
49 6
Typical instructions with 8 and 10 operands are floating point
arithmetic and multiply-accumulate instructions like:
%83:vgpr_32 = V_MUL_F32_e64 0, killed %82:vgpr_32, 0, killed %81:vgpr_32, 0, 0, implicit $exec
%330:vgpr_32 = V_MAC_F32_e64 0, killed %327:vgpr_32, 0, killed %329:sgpr_32, 0, %328:vgpr_32(tied-def 0), 0, 0, implicit $exec
Differential Revision: https://reviews.llvm.org/D70301
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py')
0 files changed, 0 insertions, 0 deletions
