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| author | Jessica Paquette <jpaquette@apple.com> | 2019-07-23 16:09:42 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-07-23 16:09:42 +0000 |
| commit | 2b404d01e82692b3085a2b1fdfd24f8d2a9739a2 (patch) | |
| tree | bfb049e1fc7362309625efcaa58ae1cd0253e1a2 /lldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py | |
| parent | 123f6ff299ea64db9307324c9002db5c68433720 (diff) | |
| download | bcm5719-llvm-2b404d01e82692b3085a2b1fdfd24f8d2a9739a2.tar.gz bcm5719-llvm-2b404d01e82692b3085a2b1fdfd24f8d2a9739a2.zip | |
[GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes
When we select the XRO variants of loads, we can pull in very specific shifts
(of the size of an element). E.g.
```
ldr x1, [x2, x3, lsl #3]
```
This teaches GISel to handle these when they're coming from shifts
specifically.
This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg`
which recognizes this pattern.
This also packs this up with `selectAddrModeRegisterOffset` into
`selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO`
in AArch64ISelDAGtoDAG.
Also update load-addressing-modes to show that all of the cases here work.
Differential Revision: https://reviews.llvm.org/D65119
llvm-svn: 366819
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py')
0 files changed, 0 insertions, 0 deletions
