Revert this patch; I was emailing with Eugene and they have some other changes going

in today and don't want the two changes to confuse the situation with the build bots.
I'll commit tomorrow once they're known good.

llvm-svn: 313934

1 files changed, 10 insertions, 12 deletions

diff --git a/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py b/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py
index a19cc5c375f..49a78888ad8 100644
--- a/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py
+++ b/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py
@@ -76,18 +76,17 @@ class RegistersIteratorTestCase(TestBase):
 
                     REGs = lldbutil.get_ESRs(frame)
                     if self.platformIsDarwin():
-                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
-                            num = len(REGs)
+                        num = len(REGs)
+                        if self.TraceOn():
+                            print(
+                                "\nNumber of exception state registers: %d" %
+                                num)
+                        for reg in REGs:
+                            self.assertTrue(reg)
                             if self.TraceOn():
                                 print(
-                                    "\nNumber of exception state registers: %d" %
-                                    num)
-                            for reg in REGs:
-                                self.assertTrue(reg)
-                                if self.TraceOn():
-                                    print(
-                                        "%s => %s" %
-                                        (reg.GetName(), reg.GetValue()))
+                                    "%s => %s" %
+                                    (reg.GetName(), reg.GetValue()))
                     else:
                         self.assertIsNone(REGs)
 
@@ -100,8 +99,7 @@ class RegistersIteratorTestCase(TestBase):
                     REGs = lldbutil.get_registers(
                         frame, "Exception State Registers")
                     if self.platformIsDarwin():
-                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
-                            self.assertIsNotNone(REGs)
+                        self.assertIsNotNone(REGs)
                     else:
                         self.assertIsNone(REGs)