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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2018-12-20 14:24:17 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2018-12-20 14:24:17 +0000
commit380bece7af2188a91bb8acebcacc684d4cbbdb3d (patch)
treefc7dabf8d8a484fa9652a14a5630e8155c28fe14 /lldb/packages/Python/lldbsuite/test/python_api/interpreter
parent84980f42be98dacae286f1ae270f247ccb43fbc1 (diff)
downloadbcm5719-llvm-380bece7af2188a91bb8acebcacc684d4cbbdb3d.tar.gz
bcm5719-llvm-380bece7af2188a91bb8acebcacc684d4cbbdb3d.zip
[SystemZ] "Generic" vector assembler instructions shoud clobber CC
There are several vector instructions which may or may not set the condition code register, depending on the value of an argument. For codegen, we use two versions of the instruction, one that sets CC and one that doesn't, which hard-code appropriate values of that argument. But we also have a "generic" version of the instruction that is used for the assembler/disassembler. These generic versions should always be considered to clobber CC just to be safe. llvm-svn: 349761
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