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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-05-02 18:12:19 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-05-02 18:12:19 +0000 |
| commit | 9aaf9233768396b8c2b9315a2fc9df64dfb3bf81 (patch) | |
| tree | db67d3d0d6ff6bf0d144fc143be5aba789bf0c45 /lldb/packages/Python/lldbsuite/test/python_api/interpreter/main.c | |
| parent | 32e20b80c692cb5f82daae648974bec259869c93 (diff) | |
| download | bcm5719-llvm-9aaf9233768396b8c2b9315a2fc9df64dfb3bf81.tar.gz bcm5719-llvm-9aaf9233768396b8c2b9315a2fc9df64dfb3bf81.zip | |
[Hexagon] Don't ignore mult-cycle latency information
The compiler was generating code that ends up ignoring a multiple
latency dependence between two instructions by scheduling the
intructions in back-to-back packets.
The packetizer needs to end a packet if the latency of the current
current insruction and the source in the previous packet is
greater than 1 cycle. This case occurs when there is still room in
the current packet, but scheduling the instruction causes a stall.
Instead, the packetizer should start a new packet. Also, if the
current packet already contains a stall, then it is okay to add
another instruction to the packet that also causes a stall. This
occurs when there are no instructions that can be scheduled in
between the producer and consumer instructions.
This patch changes the latency for loads to 2 cycles from 3 cycles.
This change refects that a load only needs to be separated by
one extra packet to eliminate the stall.
Patch by Ikhlas Ajbar.
llvm-svn: 301954
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/interpreter/main.c')
0 files changed, 0 insertions, 0 deletions
