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| author | Craig Topper <craig.topper@intel.com> | 2019-09-30 18:43:44 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-30 18:43:44 +0000 |
| commit | 3405237f77111946db90d986f2b5d9b9f8cae8a1 (patch) | |
| tree | 00f694bc1843339e4dc5a812b6e0a6ca21f86eac /lldb/packages/Python/lldbsuite/test/python_api/interpreter/main.c | |
| parent | 8216414fd12b43de1b303a904a8cc9ef5b0a2e5f (diff) | |
| download | bcm5719-llvm-3405237f77111946db90d986f2b5d9b9f8cae8a1.tar.gz bcm5719-llvm-3405237f77111946db90d986f2b5d9b9f8cae8a1.zip | |
[X86] Mask off upper bits of splat element in LowerBUILD_VECTORvXi1 when forming a SELECT.
The i1 scalar would have been type legalized to i8, but that
doesn't guarantee anything about the upper bits. If we're going
to use it as condition we need to make sure the upper bits are 0.
I've special cased ISD::SETCC conditions since that should
guarantee zero upper bits. We could go further and use
computeKnownBits, but we have no tests that would need that.
Fixes PR43507.
llvm-svn: 373246
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/interpreter/main.c')
0 files changed, 0 insertions, 0 deletions
