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| author | Justin Hibbits <jrh29@alumni.cwru.edu> | 2019-07-17 12:30:04 +0000 |
|---|---|---|
| committer | Justin Hibbits <jrh29@alumni.cwru.edu> | 2019-07-17 12:30:04 +0000 |
| commit | 5214956eaaa10a92794514558525ef6934486e90 (patch) | |
| tree | b7080dbacb5ef94bab679ab323430d5daa0dcd8e /lldb/packages/Python/lldbsuite/test/python_api/interpreter/TestRunCommandInterpreterAPI.py | |
| parent | 1e62635d0551578bf3899d2a1f4c835e30f2eed8 (diff) | |
| download | bcm5719-llvm-5214956eaaa10a92794514558525ef6934486e90.tar.gz bcm5719-llvm-5214956eaaa10a92794514558525ef6934486e90.zip | |
PowerPC/SPE: Fix load/store handling for SPE
Summary:
Pointed out in a comment for D49754, register spilling will currently
spill SPE registers at almost any offset. However, the instructions
`evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256
(unsigned) bytes from the base register, as the offset must fix into a
5-bit offset, which ranges from 0-31 (indexed in double-words).
The update to the register spill test is taken partially from the test
case shown in D49754.
Additionally, pointed out by Kei Thomsen, globals will currently use
evldd/evstdd, though the offset isn't known at compile time, so may
exceed the 8-bit (unsigned) offset permitted. This fixes that as well,
by forcing it to always use evlddx/evstddx when accessing globals.
Part of the patch contributed by Kei Thomsen.
Reviewers: nemanjai, hfinkel, joerg
Subscribers: kbarton, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54409
llvm-svn: 366318
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/interpreter/TestRunCommandInterpreterAPI.py')
0 files changed, 0 insertions, 0 deletions
