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authorCraig Topper <craig.topper@intel.com>2019-08-18 06:28:06 +0000
committerCraig Topper <craig.topper@intel.com>2019-08-18 06:28:06 +0000
commit74168ded0399a30fe9cf4d73a28a6045cc685088 (patch)
treec6e3e0730e1172549a6f68fc3380f05aac8ad45c /lldb/packages/Python/lldbsuite/test/python_api/breakpoint/TestBreakpointAPI.py
parentf43106e341d16448921b2186ae225a859c7b5aa8 (diff)
downloadbcm5719-llvm-74168ded0399a30fe9cf4d73a28a6045cc685088.tar.gz
bcm5719-llvm-74168ded0399a30fe9cf4d73a28a6045cc685088.zip
[TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
These were recently made simple types. This restores their behavior back to something like their EVT legalization. We might be able to fix the code in type legalization where the assert was failing, but I didn't investigate too much as I had already looked at the computeRegisterProperties code during the review for v3i16/v3f16. Most of the test changes restore the X86 codegen back to what it looked like before the recent change. The test case in vec_setcc.ll and is a reduced version of the reproducer from the fuzzer. Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=16490 llvm-svn: 369205
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