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| author | David Green <david.green@arm.com> | 2019-09-29 08:38:48 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-09-29 08:38:48 +0000 |
| commit | 120a5e9a745f931d805d63c6c5313a1aa24d98f5 (patch) | |
| tree | 98f25b4efe8acd346816f698e468bc9d43be98aa /lldb/packages/Python/lldbsuite/test/python_api/breakpoint/TestBreakpointAPI.py | |
| parent | 9bc1c6ecc5682c241e09c59e3c3e3a1fc7f0e7f5 (diff) | |
| download | bcm5719-llvm-120a5e9a745f931d805d63c6c5313a1aa24d98f5.tar.gz bcm5719-llvm-120a5e9a745f931d805d63c6c5313a1aa24d98f5.zip | |
[ARM] Cortex-M4 schedule additions
This is an attempt to fill in some of the missing instructions from the
Cortex-M4 schedule, and make it easier to do the same for other ARM cpus.
- Some instructions are marked as hasNoSchedulingInfo as they are pseudos or
otherwise do not require scheduling info
- A lot of features have been marked not supported
- Some WriteRes's have been added for cvt instructions.
- Some extra instruction latencies have been added, notably by relaxing the
regex for dsp instruction to catch more cases, and some fp instructions.
This goes a long way to get the CompleteModel working for this CPU. It does not
go far enough as to get all scheduling info for all output operands correct.
Differential Revision: https://reviews.llvm.org/D67957
llvm-svn: 373163
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/breakpoint/TestBreakpointAPI.py')
0 files changed, 0 insertions, 0 deletions
