diff options
| author | Guozhi Wei <carrot@google.com> | 2017-05-11 22:17:35 +0000 |
|---|---|---|
| committer | Guozhi Wei <carrot@google.com> | 2017-05-11 22:17:35 +0000 |
| commit | 22e7da9597a267165ee03cbabd31c1e4c13c5cb9 (patch) | |
| tree | 5e9c276b36bf1155394ead773501a7db7d205fd6 /lldb/packages/Python/lldbsuite/test/lang/cpp/namespace/main.cpp | |
| parent | 09e91ac6ab8a184d92100e3b1a1c4b6a0b8dc47a (diff) | |
| download | bcm5719-llvm-22e7da9597a267165ee03cbabd31c1e4c13c5cb9.tar.gz bcm5719-llvm-22e7da9597a267165ee03cbabd31c1e4c13c5cb9.zip | |
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0
According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.
This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.
Differential Revision: https://reviews.llvm.org/D32880
llvm-svn: 302834
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/cpp/namespace/main.cpp')
0 files changed, 0 insertions, 0 deletions
