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| author | Craig Topper <craig.topper@intel.com> | 2017-09-27 18:36:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-27 18:36:45 +0000 |
| commit | 05f71dd0367195ed3cd319104d8efc9a9128e174 (patch) | |
| tree | d5e18cd127935cd8cfb294637f18a47697ec9c6b /lldb/packages/Python/lldbsuite/test/lang/cpp/dynamic-value/pass-to-base.cpp | |
| parent | 102c333d9a5da87a34dbff8ea84c025db5fb5278 (diff) | |
| download | bcm5719-llvm-05f71dd0367195ed3cd319104d8efc9a9128e174.tar.gz bcm5719-llvm-05f71dd0367195ed3cd319104d8efc9a9128e174.zip | |
[X86] In combineLoopSADPattern, pad result with zeros and use full size add instead of using a smaller add and inserting.
In some cases the result psadbw is smaller than the type of the add that started the match. Currently in these cases we are using a smaller add and inserting the result.
If we instead combine the psadbw with zeros and use the full size add we can take advantage of implicit zeroing we get if we emit a narrower move before the add.
In a future patch, I want to make isel aware that the psadbw itself already zeroed the upper bits and remove the move entirely.
Differential Revision: https://reviews.llvm.org/D37453
llvm-svn: 314331
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/cpp/dynamic-value/pass-to-base.cpp')
0 files changed, 0 insertions, 0 deletions
