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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-03 10:15:46 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-03 10:15:46 +0000 |
| commit | dc5e081b93f9633d95aef7a3c62fb20170fd262f (patch) | |
| tree | 9456412ffd14ed52d579b1eb1c561e0205773173 /lldb/packages/Python/lldbsuite/test/lang/cpp/dynamic-value/TestCppValueCast.py | |
| parent | a99154bb126185c6c924d23e43200e75d7a2b736 (diff) | |
| download | bcm5719-llvm-dc5e081b93f9633d95aef7a3c62fb20170fd262f.tar.gz bcm5719-llvm-dc5e081b93f9633d95aef7a3c62fb20170fd262f.zip | |
[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Summary:
Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)
Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41441
llvm-svn: 321699
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/cpp/dynamic-value/TestCppValueCast.py')
0 files changed, 0 insertions, 0 deletions
