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| author | Craig Topper <craig.topper@intel.com> | 2019-09-11 23:54:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-11 23:54:36 +0000 |
| commit | 635d383fad2baef4cb4b241c8dd31c91913c0f32 (patch) | |
| tree | 6b4dc58b7030432c7a9cd58db71dbde494c8de65 /lldb/packages/Python/lldbsuite/test/lang/cpp/class_static | |
| parent | 55d86f04c737a9f9791500d5758af17e73558229 (diff) | |
| download | bcm5719-llvm-635d383fad2baef4cb4b241c8dd31c91913c0f32.tar.gz bcm5719-llvm-635d383fad2baef4cb4b241c8dd31c91913c0f32.zip | |
[X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.
AVX512 instructions can cause a frequency drop on these CPUs. This
can negate the performance gains from using wider vectors. Enabling
prefer-vector-width=256 will prevent generation of zmm registers
unless explicit 512 bit operations are used in the original source
code.
I believe gcc and icc both do something similar to this by default.
Differential Revision: https://reviews.llvm.org/D67259
llvm-svn: 371694
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/cpp/class_static')
0 files changed, 0 insertions, 0 deletions
