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authorDaniel Sanders <daniel.sanders@imgtec.com>2016-06-16 10:20:59 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2016-06-16 10:20:59 +0000
commitde7816b0cd3ffbd9775681c408298febe4c10fe3 (patch)
treeb87eea33d2ad56a884f14e805d373caea0fbbae8 /lldb/packages/Python/lldbsuite/test/lang/cpp/breakpoint-commands/nested.cpp
parentfa4d90d5aa7653aac7b309120b1aea236afcfa1e (diff)
downloadbcm5719-llvm-de7816b0cd3ffbd9775681c408298febe4c10fe3.tar.gz
bcm5719-llvm-de7816b0cd3ffbd9775681c408298febe4c10fe3.zip
[mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores.
Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/cpp/breakpoint-commands/nested.cpp')
0 files changed, 0 insertions, 0 deletions
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