diff options
| author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-08-28 18:54:10 +0000 |
|---|---|---|
| committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-08-28 18:54:10 +0000 |
| commit | 6b4d343e1365ac1e8f04659216d5b190f90b4694 (patch) | |
| tree | a12ea85006e63659c4726b768ed79ac7276ee7f0 /lldb/packages/Python/lldbsuite/test/lang/c/bitfields/TestBitfields.py | |
| parent | adb6da10b81d35008178826adfc678275e776c9d (diff) | |
| download | bcm5719-llvm-6b4d343e1365ac1e8f04659216d5b190f90b4694.tar.gz bcm5719-llvm-6b4d343e1365ac1e8f04659216d5b190f90b4694.zip | |
[GISel]: Add missing opcodes for overflow intrinsics
https://reviews.llvm.org/D51197
Currently, IRTranslator (and GISel) seems to be arbitrarily picking
which overflow intrinsics get mapped into opcodes which either have a
carry as an input or not.
For intrinsics such as Intrinsic::uadd_with_overflow, translate it to an
opcode (G_UADDO) which doesn't have any carry inputs (similar to LLVM
IR).
This patch adds 4 missing opcodes for completeness - G_UADDO, G_USUBO,
G_SSUBE and G_SADDE.
llvm-svn: 340865
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lang/c/bitfields/TestBitfields.py')
0 files changed, 0 insertions, 0 deletions
