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| author | Jason Molenda <jmolenda@apple.com> | 2017-09-21 23:02:56 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 2017-09-21 23:02:56 +0000 |
| commit | 2d5d71c0614a09aab981aa614264581bd83e4249 (patch) | |
| tree | cd4499b83a6fc093626c6b4eb47011bab5f2702f /lldb/packages/Python/lldbsuite/test/functionalities/register | |
| parent | 540a8c7fad15ba51c12a61e10a929f247dcd49ff (diff) | |
| download | bcm5719-llvm-2d5d71c0614a09aab981aa614264581bd83e4249.tar.gz bcm5719-llvm-2d5d71c0614a09aab981aa614264581bd83e4249.zip | |
Revert this patch; I was emailing with Eugene and they have some other changes going
in today and don't want the two changes to confuse the situation with the build bots.
I'll commit tomorrow once they're known good.
llvm-svn: 313934
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/functionalities/register')
| -rw-r--r-- | lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py | 35 |
1 files changed, 2 insertions, 33 deletions
diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py index 33680ca91d6..fe6ce2c25a3 100644 --- a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py +++ b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py @@ -45,7 +45,7 @@ class RegisterCommandsTestCase(TestBase): self.runCmd("register read xmm0") self.runCmd("register read ymm15") # may be available self.runCmd("register read bnd0") # may be available - elif self.getArchitecture() in ['arm', 'armv7', 'arm64']: + elif self.getArchitecture() in ['arm']: self.runCmd("register read s0") self.runCmd("register read q15") # may be available @@ -84,10 +84,7 @@ class RegisterCommandsTestCase(TestBase): if self.getArchitecture() in ['amd64', 'i386', 'x86_64']: gpr = "eax" vector = "xmm0" - elif self.getArchitecture() in ['arm64', 'aarch64']: - gpr = "w0" - vector = "v0" - elif self.getArchitecture() in ['arm', 'armv7']: + elif self.getArchitecture() in ['arm']: gpr = "r0" vector = "q0" @@ -320,34 +317,6 @@ class RegisterCommandsTestCase(TestBase): ("xmm15", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", False)) - elif self.getArchitecture() in ['arm64', 'aarch64']: - reg_list = [ - # reg value - # must-have - ("fpsr", "0xfbf79f9f", True), - ("s0", "1.25", True), - ("s31", "0.75", True), - ("d1", "123", True), - ("d17", "987", False), - ("v1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True), - ("v14", - "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", - False), - ] - elif self.getArchitecture() in ['armv7', 'armv7k']: - reg_list = [ - # reg value - # must-have - ("fpsr", "0xfbf79f9f", True), - ("s0", "1.25", True), - ("s31", "0.75", True), - ("d1", "123", True), - ("d17", "987", False), - ("q1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True), - ("q14", - "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", - False), - ] elif self.getArchitecture() in ['arm']: reg_list = [ # reg value |
