Initial patchset to get the testsuite running against armv7 and arm64 iOS devices.

Normal customer devices won't be able to run these devices, we're hoping to get
a public facing bot set up at some point.  Both devices pass the testsuite without
any errors or failures.

I have seen some instability with the armv7 test runs, I may submit additional patches
to address this.  arm64 looks good.

I'll be watching the bots for the rest of today; if any problems are introduced by
this patch I'll revert it - if anyone sees a problem with their bot that I don't
see, please do the same.  I know it's a rather large patch.

One change I had to make specifically for iOS devices was that debugserver can't 
create files.  There were several tests that launch the inferior process redirecting
its output to a file, then they retrieve the file.  They were not trying to test
file redirection in these tests, so I rewrote those to write their output to a file
directly.

llvm-svn: 314038

1 files changed, 33 insertions, 2 deletions

diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
index fe6ce2c25a3..8c33687f688 100644
--- a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
@@ -45,7 +45,7 @@ class RegisterCommandsTestCase(TestBase):
             self.runCmd("register read xmm0")
             self.runCmd("register read ymm15")  # may be available
             self.runCmd("register read bnd0")  # may be available
-        elif self.getArchitecture() in ['arm']:
+        elif self.getArchitecture() in ['arm', 'armv7', 'arm64']:
             self.runCmd("register read s0")
             self.runCmd("register read q15")  # may be available
 
@@ -84,7 +84,10 @@ class RegisterCommandsTestCase(TestBase):
         if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
             gpr = "eax"
             vector = "xmm0"
-        elif self.getArchitecture() in ['arm']:
+        elif self.getArchitecture() in ['arm64', 'aarch64']:
+            gpr = "w0"
+            vector = "v0"
+        elif self.getArchitecture() in ['arm', 'armv7']:
             gpr = "r0"
             vector = "q0"
 
@@ -317,6 +320,34 @@ class RegisterCommandsTestCase(TestBase):
                     ("xmm15",
                      "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
                      False))
+        elif self.getArchitecture() in ['arm64', 'aarch64']:
+            reg_list = [
+                # reg      value
+                # must-have
+                ("fpsr", "0xfbf79f9f", True),
+                ("s0", "1.25", True),
+                ("s31", "0.75", True),
+                ("d1", "123", True),
+                ("d17", "987", False),
+                ("v1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True),
+                ("v14",
+                 "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
+                 False),
+            ]
+        elif self.getArchitecture() in ['armv7', 'armv7k'] and self.platformIsDarwin():
+            reg_list = [
+                # reg      value
+                # must-have
+                ("fpsr", "0xfbf79f9f", True),
+                ("s0", "1.25", True),
+                ("s31", "0.75", True),
+                ("d1", "123", True),
+                ("d17", "987", False),
+                ("q1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True),
+                ("q14",
+                 "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
+                 False),
+            ]
         elif self.getArchitecture() in ['arm']:
             reg_list = [
                 # reg      value