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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-08-01 16:04:29 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-08-01 16:04:29 +0000 |
| commit | 0620cf11ec2d5085117768ab437d2f24ef006419 (patch) | |
| tree | 948c4d4918cb49463b57674f55ffb87fdab8705c /lldb/packages/Python/lldbsuite/test/functionalities/multidebugger_commands/TestMultipleDebuggersCommands.py | |
| parent | 66ce04f26113cfc8ca925613f72e3f9a0c1498e7 (diff) | |
| download | bcm5719-llvm-0620cf11ec2d5085117768ab437d2f24ef006419.tar.gz bcm5719-llvm-0620cf11ec2d5085117768ab437d2f24ef006419.zip | |
[mips] Fix lowering load/store instruction in PIC case
If an operand of the `lw/sw` instructions is a symbol, these instructions
incorrectly lowered using not-position-independent chain of commands.
For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16`
and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates
position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16`
relocations.
This patch provides a fix for the bug by handling PIC case separately in
the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain
of PIC instructions to load a symbol address into a register and then
load the address content.
The fix is not optimal and does not fix all PIC-related problems. This
is a task for subsequent patches.
Differential Revision: https://reviews.llvm.org/D65524
llvm-svn: 367580
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/functionalities/multidebugger_commands/TestMultipleDebuggersCommands.py')
0 files changed, 0 insertions, 0 deletions
