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| author | Craig Topper <craig.topper@intel.com> | 2018-05-17 16:29:52 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-05-17 16:29:52 +0000 |
| commit | bd332588bd3997fec40447c9bc98706085145b3c (patch) | |
| tree | a68ba4e461f34c0a34125e9c8389b1048565c024 /lldb/packages/Python/lldbsuite/test/expression_command/timeout/wait-a-while.cpp | |
| parent | e389ea0e3ed2164b237177d3369c0ef1a61236ae (diff) | |
| download | bcm5719-llvm-bd332588bd3997fec40447c9bc98706085145b3c.tar.gz bcm5719-llvm-bd332588bd3997fec40447c9bc98706085145b3c.zip | |
[InstCombine] Propagate the nsw/nuw flags from the add in the 'shifty' abs pattern to the sub in the select version.
According to alive this is valid. I'm hoping to use this to make an assumption that the sign bit is zero after this sequence. The only way it wouldn't be is if the input was INT__MIN, but by preserving the flags we can make doing this to INT_MIN UB.
The nuw flags is weird because it creates such a contradiction that the original number would have to be positive meaning we could remove the select entirely, but we don't get that far.
Differential Revision: https://reviews.llvm.org/D46988
llvm-svn: 332623
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/timeout/wait-a-while.cpp')
0 files changed, 0 insertions, 0 deletions
