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authorTim Northover <tnorthover@apple.com>2017-06-12 20:49:53 +0000
committerTim Northover <tnorthover@apple.com>2017-06-12 20:49:53 +0000
commit7a61316e89862e12eda0a1e92619ff17897f929f (patch)
tree03ffcab33b69ee00353021fac0bcbf54c81dafb2 /lldb/packages/Python/lldbsuite/test/expression_command/macros/main.cpp
parentd334cebac4ca2c51677b415526d1e23476298710 (diff)
downloadbcm5719-llvm-7a61316e89862e12eda0a1e92619ff17897f929f.tar.gz
bcm5719-llvm-7a61316e89862e12eda0a1e92619ff17897f929f.zip
AArch64: don't try to emit an add (shifted reg) for SP.
The "Add/sub (shifted reg)" instructions use the 31 encoding for xzr and wzr rather than the SP, so we need to use different variants. Situations where this actually comes up are rare enough (see test-case) that I think falling back to DAG is fine. llvm-svn: 305230
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/macros/main.cpp')
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