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| author | Craig Topper <craig.topper@gmail.com> | 2016-12-09 07:57:21 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-12-09 07:57:21 +0000 |
| commit | 38b1b5d44f979a38b281fcb5efa24666bace5e6c (patch) | |
| tree | 12470303cfe22e4cb8f728db171c1804e1d188b0 /lldb/packages/Python/lldbsuite/test/expression_command/macros/TestMacros.py | |
| parent | 18ae0f68f80ec9a66ed609521f3363e47558fe71 (diff) | |
| download | bcm5719-llvm-38b1b5d44f979a38b281fcb5efa24666bace5e6c.tar.gz bcm5719-llvm-38b1b5d44f979a38b281fcb5efa24666bace5e6c.zip | |
[X86] Modify patterns from memory form of RCP/RSQRT/SQRT intrinsics to only allow (scalar_to_vector (loadf32/load64)) instead of anything that sse_load_f32/f64 can match.
sse_load_f32/f64 can also match loads that are zero extended to vectors. We shouldn't match that because we wouldn't be able to get the instruction to zero the upper bits like the intrinsic semantics would require for such a case.
There is a test case that does depend on this behavior.
llvm-svn: 289193
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/macros/TestMacros.py')
0 files changed, 0 insertions, 0 deletions
