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| author | Craig Topper <craig.topper@intel.com> | 2018-12-04 04:51:07 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-12-04 04:51:07 +0000 |
| commit | 35585aff34837f227f9103704af48eaad810df13 (patch) | |
| tree | dc26f2d004299cdb7f9d8a2424ceab6c40a78bd8 /lldb/packages/Python/lldbsuite/test/expression_command/ir-interpreter/TestIRInterpreter.py | |
| parent | 5c43abcf2df2276f7fe714998190fdb3a8696d44 (diff) | |
| download | bcm5719-llvm-35585aff34837f227f9103704af48eaad810df13.tar.gz bcm5719-llvm-35585aff34837f227f9103704af48eaad810df13.zip | |
[X86] Remove custom DAG combine for SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG.
We only needed this because it provided really aggressive constant folding even through constant pool entries created from build_vectors. The main case was for vXi8 MULH legalization which was happening as part of legalize DAG instead of as part of legalize vector ops. Now its part of vector op legalization and we've added special handling for build vectors of all constants there. This has removed the need for this code on the list tests we have.
llvm-svn: 348237
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/ir-interpreter/TestIRInterpreter.py')
0 files changed, 0 insertions, 0 deletions
