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| author | Jessica Paquette <jpaquette@apple.com> | 2019-07-18 21:50:11 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-07-18 21:50:11 +0000 |
| commit | 7a1dcc5ff1da38f950f77ee22c0e843bdb6c5eb5 (patch) | |
| tree | 6bf83e06d888df646254478491140411ae6a773d /lldb/packages/Python/lldbsuite/test/expression_command/inline-namespace/main.cpp | |
| parent | 50057f328870e0ecc4975cd4ef46b2fd6221d999 (diff) | |
| download | bcm5719-llvm-7a1dcc5ff1da38f950f77ee22c0e843bdb6c5eb5.tar.gz bcm5719-llvm-7a1dcc5ff1da38f950f77ee22c0e843bdb6c5eb5.zip | |
[GlobalISel][AArch64] Add support for base register + offset register loads
Add support for folding G_GEPs into loads of the form
```
ldr reg, [base, off]
```
when possible. This can save an add before the load. Currently, this is only
supported for loads of 64 bits into 64 bit registers.
Add a new addressing mode function, `selectAddrModeRegisterOffset` which
performs this folding when it is profitable.
Also add a test for addressing modes for G_LOAD.
Differential Revision: https://reviews.llvm.org/D64944
llvm-svn: 366503
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/inline-namespace/main.cpp')
0 files changed, 0 insertions, 0 deletions
