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authorJessica Paquette <jpaquette@apple.com>2019-07-18 21:50:11 +0000
committerJessica Paquette <jpaquette@apple.com>2019-07-18 21:50:11 +0000
commit7a1dcc5ff1da38f950f77ee22c0e843bdb6c5eb5 (patch)
tree6bf83e06d888df646254478491140411ae6a773d /lldb/packages/Python/lldbsuite/test/expression_command/inline-namespace/main.cpp
parent50057f328870e0ecc4975cd4ef46b2fd6221d999 (diff)
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[GlobalISel][AArch64] Add support for base register + offset register loads
Add support for folding G_GEPs into loads of the form ``` ldr reg, [base, off] ``` when possible. This can save an add before the load. Currently, this is only supported for loads of 64 bits into 64 bit registers. Add a new addressing mode function, `selectAddrModeRegisterOffset` which performs this folding when it is profitable. Also add a test for addressing modes for G_LOAD. Differential Revision: https://reviews.llvm.org/D64944 llvm-svn: 366503
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/inline-namespace/main.cpp')
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