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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-08 08:52:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-08 08:52:31 +0000 |
| commit | f6ee94c1c6a2579de732c82a3d4221237c455c05 (patch) | |
| tree | 428b6f7caf6a4a39bcb301487b4f69f933d15ee8 /lldb/packages/Python/lldbsuite/test/expression_command/expr-in-syscall/main.cpp | |
| parent | c78ccbdefb921b86b816275a65fbe635d596a028 (diff) | |
| download | bcm5719-llvm-f6ee94c1c6a2579de732c82a3d4221237c455c05.tar.gz bcm5719-llvm-f6ee94c1c6a2579de732c82a3d4221237c455c05.zip | |
DAG: Add computeKnownBitsForFrameIndex
Some of the AMDGPU stack addressing modes require knowing the sign
bit is zero. We used to accomplish this by custom lowering
frame indexes, and then putting an AssertZext around a
TargetFrameIndex. This required specifically looking for
the AssextZext + frame index pattern which was moderately
disgusting. The same could probably be accomplished
with a target specific node, but would still
require special handling of frame indexes.
llvm-svn: 317671
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/expr-in-syscall/main.cpp')
0 files changed, 0 insertions, 0 deletions
