diff options
| author | Oliver Stannard <oliver.stannard@arm.com> | 2016-06-08 15:26:34 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2016-06-08 15:26:34 +0000 |
| commit | b3378e2f3cd07a8a3e36b8b01e5c7222e38f6f56 (patch) | |
| tree | 73e1e955fdfc8051ee3a361a893c0d7776d818d6 /lldb/packages/Python/lldbsuite/test/expression_command/expr-in-syscall/TestExpressionInSyscall.py | |
| parent | c564701fbd62bbd47b001564ace2649c19ae92ce (diff) | |
| download | bcm5719-llvm-b3378e2f3cd07a8a3e36b8b01e5c7222e38f6f56.tar.gz bcm5719-llvm-b3378e2f3cd07a8a3e36b8b01e5c7222e38f6f56.zip | |
[ARM] MSR instructions implicitly set CPSR
The MSR instructions can write to the CPSR, but we did not model this
fact, so we could emit them in the middle of IT blocks, changing the
condition flags for later instructions in the block.
The tests use two calls to llvm.write_register.i32 because it is valid
to use these instructions at the end of an IT block, which if conversion
does do in some cases. With two calls, the first clobbers the flags, so
a branch has to be used to make the second one conditional.
Differential Revision: http://reviews.llvm.org/D21139
llvm-svn: 272154
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/expr-in-syscall/TestExpressionInSyscall.py')
0 files changed, 0 insertions, 0 deletions
