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author | Florian Hahn <florian.hahn@arm.com> | 2017-11-07 16:45:48 +0000 |
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committer | Florian Hahn <florian.hahn@arm.com> | 2017-11-07 16:45:48 +0000 |
commit | 91f11e5ad1eecc92acce539cd2de223ebe841f1a (patch) | |
tree | d5ec40156912b974cb0630b9efe8008448f20f8f /lldb/packages/Python/lldbsuite/test/expression_command/call-function | |
parent | 612d693c64ce3e53854f0ecd92210515c5036977 (diff) | |
download | bcm5719-llvm-91f11e5ad1eecc92acce539cd2de223ebe841f1a.tar.gz bcm5719-llvm-91f11e5ad1eecc92acce539cd2de223ebe841f1a.zip |
[AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support
Patch [3/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.
To summarise, this patch adds:
* SVE register definitions
* Methods to parse SVE register operands
* Methods to print SVE register operands
* RegKind SVEDataVector to distinguish it from other data types like scalar register or Neon vector.
* k_SVEDataRegister and SVEDataRegOp to describe SVE registers (which will be extended by further patches with e.g. ElementWidth and the shift-extend type).
Patch by Sander De Smalen.
Reviewed by: rengolin
Differential Revision: https://reviews.llvm.org/D39089
llvm-svn: 317590
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/call-function')
0 files changed, 0 insertions, 0 deletions