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| author | Craig Topper <craig.topper@intel.com> | 2017-12-04 05:38:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-04 05:38:42 +0000 |
| commit | 67217d7eb474982c34d807acae60708466b9f519 (patch) | |
| tree | 75d68ea9c6645cb1148106ca37da43f8d9d8d8c2 /lldb/packages/Python/lldbsuite/test/expression_command/call-function/main.cpp | |
| parent | a565a7b9b835656746d82425721d0f0eb69e3113 (diff) | |
| download | bcm5719-llvm-67217d7eb474982c34d807acae60708466b9f519.tar.gz bcm5719-llvm-67217d7eb474982c34d807acae60708466b9f519.zip | |
[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat constant shift amount.
If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this
fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero.
llvm-svn: 319639
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/call-function/main.cpp')
0 files changed, 0 insertions, 0 deletions
